module GRF(
        input [4:0] reg1,
        input [4:0] reg2,
        input [4:0] wr,
        input [31:0] wd,
        input clk,
        input rst,
        input RegWrite,
        input [31:0] pc,
        output [31:0] read1,
        output [31:0] read2
    );
    reg [31:0] registersFile[0:31];
    integer i=0;
    always @(posedge clk) begin
        if(rst) begin
            for(i=0;i<32;i=i+1) begin
                registersFile[i]<=32'd0;
            end
        end
        else begin
            if(RegWrite) begin
                if(wr!=5'd0) begin
                    registersFile[wr]<=wd;
                    $display("@%h: $%d <= %h", pc,wr, wd);
                end
                else
                    registersFile[wr]<=registersFile[wr];
            end
        end
    end
    assign read1=registersFile[reg1];
    assign read2=registersFile[reg2];
endmodule
